Track and hold circuits (also known as sample and hold circuits) are especially useful in digital systems where an analog input signal is converted into a stream of digital values. The track and hold circuit follows the analog input signal and at predetermined intervals holds the input voltage so that it may be converted to a digital value.
FIG. 1 is a block diagram of a typical prior art track and hold circuit 10 having an input signal voltage provided at terminal 11. A clock signal is provided at a control terminal of switch 12 to control the on and off states of switch 12. During the track mode, switch 12 is on and passes the input signal to hold capacitor 13 which then charges or discharges to the input voltage. During the hold mode, switch 12 is turned off. Capacitor 13 holds the input voltage and provides the input voltage to unity gain buffer 14 which, in turn, provides the input voltage at output terminal 15.
Optimizing the performance of track and hold circuit 10 involves making undesirable compromises. First, since leakage currents in switch 12 and buffer 14 cause the voltage on capacitor 13 to droop (i.e., discharge) during hold mode, capacitor 13 should be large. If, however, high speed signals are to be followed accurately, capacitor 13 should be of a small value in order to avoid forming a low pass filter with the on-resistance of switch 12 which would undesirably restrict the input bandwidth of circuit 10. Second, increasing the input impedance of buffer 14 would advantageously minimize droop by minimizing current flow from capacitor 13 during hold mode. Such a high input impedance, however, would compromise the speed of circuit 10.
A further disadvantage of the prior art track and hold circuit of FIG. 1 is that the clock signal provided to switch 12 causes charge injection into capacitor 13 which, in turn, results in a significant pedestal error. In addition, the non-linearity of the on-resistance of MOS switch 12 causes distortion which varies according to changes in amplitude and frequency of the input signal voltage.
A track and hold circuit which overcomes many of the problems discussed above is disclosed by Kazuya Sone et al, "A 10b 100Ms/s Pipeline Subranging BiCMOS ADC", 1993 IEEE International Solid State Circuits Conference and shown in FIG. 2. Track and Hold circuit 20 includes two hold capacitors. Hold capacitor 22 holds the input voltage during hold mode, as does capacitor 12 of circuit 10, while hold capacitor 24, which is connected between output terminal 26 and the inverting terminal of buffer amplifier 28, minimizes voltage droop during hold mode.
Switch 30, which connects an input signal to capacitor 22 and buffer 28, is a bipolar current steering switch. A second bipolar current steering switch 32 is provided in parallel to hold capacitor 24. A clocking signal provided to both switches 30 and 32 simultaneously turns switches 30 and 32 on and off. The clocking signal provided to switch 32 causes charge injection into capacitor 24, resulting in a pedestal error which offsets any pedestal error caused by charge injection of hold capacitor 22.
The operation of track and hold circuit 20 is as follows. An input signal V.sub.in is applied to circuit 20 at the base of input transistor Q1 (terminal 42). A track mode clock signal (CK.sub.T) is provided to circuit 20 at terminal 34 for turning on and off transistors Q3 and Q5. A hold mode clock signal (CK.sub.H) is provided to circuit 20 at terminal 36 for turning on and off transistors Q4 and Q6.
In track mode, CK.sub.T goes high and turns on transistors Q3 and Q5. Transistor Q3 turns on transistor Q1 and diode-connected transistors D.sub.4 and D.sub.5. Transistor Q5 turns on output transistor Q2. CK.sub.H simultaneously goes low and turns off transistors Q4 and Q6. When in its off state, transistor Q4 ensures that diode-connected transistors D1, D2, and D3 are reversed biased and thus non-conducting. Current source 38 provides a bias current 2I through transistor Q3 which is evenly divided between transistor Q1 and diodes D5 and D4, i.e., transistor Q1 and diodes D4-D5 are each biased by a current approximately equal to I. Current source 40 provides a bias current 2I through transistor Q2 via transistor Q5.
Transistors Q1 and Q2 operate as emitter followers and diodes D4 and D5 operate as voltage level shifters. The input signal voltage V.sub.in applied at input terminal 42 appears at the emitter of transistor Q2 and charges hold capacitor 22. The voltage on hold capacitor 22 accurately follows the input voltage V.sub.in at terminal 42 as can be seen from the following equation: EQU V.sub.cap22 =V.sub.in -V.sub.be,Q1 +V.sub.be,D5 +V.sub.be,D4 -V.sub.be,Q2 =V.sub.in.
Note that during track mode no current flows through transistors D1-D3.
When circuit 20 transitions to hold mode, CK.sub.T goes low and turns off transistors Q3 and Q5. Transistor Q3 turns off transistor Q1 and diodes D4 and D5 to prevent feedthrough of the input voltage V.sub.in at terminal 42. When non-conducting transistor Q5, by ensuring that no current flows from hold capacitor 22 to ground, prevents capacitor 22 from discharging during hold mode. CK.sub.H simultaneously goes high and turns on transistors Q4 and Q6. Transistor Q6 provides a path to ground for current source 40. Source 38, via transistor Q4, pulls a current I from DC source 37 and a current I through diodes D1-D3. The current I through diodes D1-D3 turns on diodes D1-D3 which, in turn, pull the base of transistor Q2 to approximately 3 V.sub.be below ground to ensure that transistor Q2 remains off during hold mode. Further, since diodes D1-D3 hold the voltage at the base of transistor Q2 constant during hold mode, any parasitic feedthrough of the input voltage V.sub.in is effectively clamped during hold mode.
During hold mode, the non-conductive states of transistors Q1 and Q2 prevent further charging of hold capacitor 22, while the non-conductive state of transistor Q5 prevents hold capacitor 22 from discharging to ground via transistor Q5. Thus, during hold mode capacitor 22 is able to maintain a substantially constant voltage which is then provided to output terminal 26 via unity gain buffer 28.
The track and hold circuit described above with reference to FIG. 2 is problematic when switching from hold mode to track mode. Since input transistor Q1 and output transistor Q2 (as well as diodes D4 and D5) are turned off during hold mode, they must be turned back on when circuit 20 transitions from hold mode to track mode. The acquisition time of these transistors undesirably limits the speed of circuit 20. Further, as input transistor Q1 switches between on and off states as circuit 20 switches between track mode and hold mode, respectively, the base current of transistor Q1 will fluctuate between zero and I/B, where B is the Beta of transistor Q1. This base current fluctuation results in undesirable voltage spikes at input terminal 42.
Thus, there is a need for a track and hold circuit which has a faster switching capability and which does not suffer from voltage spikes at its input terminal.